A collection of memory test programs for boards produced by
PTC.  These programs were taken from the various memory
board manuals but have been standardized so that they are
basically similar.  Some bugs have been removed and some
enhancements have been made to improve performance.  As
given in the source listings, the ORG statement is set for
memory address at C900H since all Sols have memory at this
address.  Note, however, that memory in this region is
'slow.'  The Sol inserts wait states for all accesses to
this memory block.  For improved performance, change the ORG
statement (and the XEQ) to some other memory area which you
know is good and running at full speed.

These tests can be used to check any memory but the Chip Maps
given by them are ordered for the layout on the various
PTC boards.  That is basically the only difference between
the tests.  The nKRA and nKRA-1 series have different chip
layouts.  For a more detailed source listing, refer to the
appropriate memory board manual.

An additional program, MTEST:S, is available to test a
single byte or block of memory.  For some reason, this
program doesn't seem to test memory from address 0000
to 0020 properly or the last few bytes near FFFF.

8KRA:S    For use with PTC's 8K static memory
16KRA:S        "        "    16K dynamic  "
16K-1:S        "        "     "     "     "    16KRA-1
32KRA:S        "        "    32K    "     "
32K-1:S        "        "     "     "     "    32KRA-1
48K-1:S        "        "    48K    "     "    48KRA-1
MTEST:S   General purpose memory test program

Note:  The K series of tests are copyrighted by Processor
       Technology Corporation.  The modifications to the
       tests (written by Joe Maguire) are not.  The source
       of the MTEST is from the SCCS magazine, Interface.